A flash device is essentially an electrically erasable programmable read only memory (EEPROM or E2PROM), which allow blocks of data to be programmed or erased at relatively high operating speeds. A flash differs from an EEPROM in that a flash is generally adapted to operate on blocks of data while an EEPROM or E2PROM has to be erased all at once, even though the EEPROM may be programmed on a byte-by-byte basis.
Today, NAND flash and NOR flash memory devices dominate the non-volatile flash memory market. A NAND flash memory is a non-linear addressed device requiring multiplexed input/output (I/O) pins for handling both data and commands. A NAND flash memory device is a serially interfaced device in which address, data, and control information are multiplexed on the same pins. As a result of its serial interface, the NAND flash memory device requires extensive I/O interfaces and drivers for handling the multiplexed I/O pins. A NAND flash memory device is typically accessed by block or page, thereby permitting, for example, 512 bytes of data to be written to or read from the device. Random access errors generated by physical degradation in the geometry of the NAND gates results in low reliability for NAND flash memory devices.
A NOR flash device is a linear addressed device, which comprises separate address and data lines. In this regard, a NOR flash device is somewhat similar to a dynamic random access memory (DRAM) device. A NOR flash memory generally comprises sufficient address pins that allow it to be memory mapped into a processor's address space, thereby allowing the NOR flash to be accessed like a read only memory (ROM). The cell structure of NAND flash is almost one-half the size of a NOR flash's cell structure and as a result, for a given die, NAND flash memory devices have a much higher packing density than NOR flash memory devices. For example, NOR flash capacities range from 1 megabyte (MB) to 4 MBs while NAND flash capacities range from 32 MBs to 512 MBs. In addition to its higher packing density and thus higher capacity, NAND flash is cheaper than NOR flash since it utilizes much smaller die size of silicon wafer than NOR flash. NOR flash memory devices also possess less than 10% of the lifespan of NAND flash memory devices.
Given today's trends in wireless communication technologies, consumer demand is constantly forcing device manufactures to create access devices such as handhelds, which store more data using less chip die size at significantly lower costs. A NAND flash memory is typically utilized in portable electronic devices/products that require a large storage capacity, which can store data when there is a loss of power. NAND flash memory is also utilized in these products/devices because of its low cost and low power consumption when compared with traditional NOR flash memory. Today, NAND flash is widely utilized in USB storage devices, MP3 players, digital answer machines, digital recorders, various kinds of memory cards including, but not limited to, compact flash cards, SmartMedia cards, and SecureDigital (SD) cards. In cellular telephones (cell phones) and personal digital assistant (PDA) type devices, for example, NAND flash may be utilized to store digitized data such as images, audio and video.
Although NAND flash possesses the highest bit densities of the various types of flash memories, is inexpensive, and has much lower power consumption than NOR flash, it has a low reliability due to runtime bad bit and prolonged access time. Unlike NOR flash, these issues of reliability with NAND flash makes it impractical to execute the computer instructions directly from the NAND flash. Notwithstanding, manufactures of NAND flash recommend the use of error correcting technology to enhance data integrity. After using error correction technology, the bad bits can be detected and corrected, thereby making the NAND flash a more practical solution for storing computer instruction and for storing data like on a hard disk, which may be managed by a file system in order to maintain data integrity.
In existing systems, error correction methodologies typically operate on a page of data of the order of 512, 1024, 2048 bytes or larger page size. Furthermore, special logic operations such as bit manipulations are required to generate the error correction codes. Accordingly, if only software is utilized to compute and/or otherwise generate the error correction codes, then a large amount of processor cycles are required because utilizing a processor for bit manipulations may be ineffective. On the other hand, if only hardware is utilized to compute the error correction codes, then additional storage is required to store the pages of data. As the page size increases, so does the amount of memory that is required for storing the page data. For embedded system applications, for example, the additional storage may be very expensive since a large gate count is required and this makes the chip very expensive.
Existing standalone chips require a large die size because the standalone chips utilizes sufficiently large storage for storing pages of data that is controlled by a programmable state machine, which is adapted to generate the error correction codes. Furthermore, processors do not provide the most optimal manner for handling bit manipulations. In instances where only software is utilized to generate error correction codes, and detect and correct errors, the software utilizes a huge amount of processing time that may block other software applications from running.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.